The present invention relates to a magnetic memory device, more specifically a magnetic memory device using resistance changes due to spin directions of a magnetic layer, and methods for reading and writing the magnetic memory device.
Recently, as a rewritable nonvolatile memory a magnetic random access memory (hereinafter called an MRAM) including magnetoresistive effect elements arranged in a matrix is noted. The MRAM uses combinations of magnetization directions of two magnetic layers to memorize information and, to read the information, detects resistance changes (i.e., current changes or voltage changes) between the resistance with the magnetization directions of the two magnetic layers being parallel with each other and the resistance with the magnetization directions of the two magnetic layers being antiparallel with each other.
As one magnetoresistive effect element forming the MRAM, a magnetic tunnel junction (hereinafter called an MTJ) element is known. The MTJ is a element includes two ferromagnetic layers laid one on the other with an insulating film formed therebetween and utilizes the phenomenon that the tunneling current flowing between the magnetic layers via the tunnel insulating film is changed due to relationships between the magnetization directions of the two ferromagnetic layers.
That is, the MTJ element has low resistance when the magnetization directions of the two ferromagnetic layers are parallel with each other and has high resistance when both are antiparallel with each other. These two states are set to be data “0” and data “1” to use the MTJ element as a memory device. The MTJ element is a memory element using changes of the element resistance, so that the resistance changes must convert to voltage or current to read the memorized information.
FIG. 17 is a circuit diagram for the method for reading the conventional magnetic memory device. In the magnetic memory device shown in FIG. 17, one MOS transistor 102 and one MTJ element 104 constitute one memory cell 100 (1T-1MTJ type). The memory cell 100 is connected to the source electrode of a MOS transistor 106. The drain electrode of the MOS transistor 106 is connected to a current source 108.
A certain bias voltage Vclamp is applied to the gate electrode of the MOS transistor 106 to keep a voltage applied to the MTJ element 104 substantially constant. In this state, current is flowed from the current source 108 to the MOS transistor 106, the MTJ element 104 and the MOS transistor 102, whereby a voltage corresponding to a resistance value of the MTJ element is outputted to the drain terminal of the MOS transistor 106. That is, when the resistance of the MTJ element 104 is high, the output voltage is high, and the output voltage is low when the resistance of the MTJ element 104 is low. Such voltage changes are amplified by a sense amplifier (not shown) to be read signals.
The read circuit shown in FIG. 17 requires a large area to accommodate a large gate width of the MOS transistor 106 and the current source 108, and the sense amplifier has a large area. Accordingly, the sense amplifier cannot be accommodated at a pitch between the bit BL and the bit line/BL. To solve this problem it is proposed to make the read circuit common among a plurality of columns.
FIG. 18 shows an example of the application of the proposal to the magnetic memory device including 2T-2MTJ type memory cells each having two MOS transistors and two MTJ elements. The magnetic memory device shown in FIG. 18 includes one read circuit 110 for a plurality of bit line pairs (adjacent bit lines BL, /BL) and a column select circuit 112 for changing over the bit line pairs. Thus, the number of the read circuits 110 is made small, and the area of the read circuits as a whole is made small.
FIG. 19 shows an example of the application of the proposal to the magnetic memory device including 1T-1MTJ type memory cells. The magnetic memory device shown in FIG. 19 includes a reference cell 120 in addition to the memory cells. A plurality of bit lines BL and a bit line connected to the reference cell 120 are connected to a read circuit 122. Select transistors are provided respectively between the respective bit lines BL and the read circuit 122, so that one bit line can be selected out of the plurality of bit lines for read. Thus, the number of the read circuits 122 is made small, and the area of the read circuit as a whole is made small.
Related arts are disclosed in, e.g., Reference 1 (Japanese published unexamined patent application No. 2001-236781), Reference 2 (Japanese published unexamined patent application No. 2001-273758), Reference 3 (Japanese published unexamined patent application No. 2003-197876, Reference 4 (Japanese published unexamined patent application No. 2004-030822), Reference 5 (Roy Scheuerlein et al., “A 10 ns read and write non-volatile memory array using a magnetic tunnel junction and FET switch in each cell”, ISSCC Dig. Tech. Papers, pp. 128-129, 2000), Reference 6 (M. Durlam et al., “A low power 1 Mbit MRAM based on 1T1MTJ bit cell integrated with copper interconnects”, Symposium on VLSI Circuits Dig. Tech. Papers, pp. 158-161, 2002), and Reference 7 (N. Tanabe et al., “A high density 1T/2C cell with Vcc/2 reference level for high stable FeRAMs”, IEDM Tech. Dig., pp. 863-866, 1997).
However, the 2T-2MJT type magnetic memory device shown in FIG. 18 includes a large number of devices forming one memory cell, which makes it difficult to improve the integration degree.
On the other hand, the 1T-1MTJ type magnetic memory device shown in FIG. 19 can increase the integration degree more easily than the magnetic memory device shown in FIG. 18. The reference cell 120 generates reference signals, so that fluctuation of the reference cell 120 directly influences the read margin. Especially, because of one reference cell 120 for a plurality of bit lines, some of the bit lines are near the reference cell 120, and others of the bit lines are remote from the reference cell 120. The fluctuation of characteristics of the MTJ elements is very influential. This makes it impossible to read by the differential amplification using pairs of adjacent bit lines, which is characteristically good against noises, resultantly with a risk of reduced noise resistance.